EDA & verification acceleration for multi-die AI designs
Key Questions
What speedups are being achieved in EDA and verification for multi-die AI designs?
Cadence-NVIDIA achieves 80x speedup for 3D-IC designs, while Synopsys-NVIDIA/Ansys/Samsung reduces STCO/3DIC time by 50% with DVD/Intel EMIB acceleration. MediaTek reports 10x gains at GTC, and ASML-Mistral delivers 120x. These shorten EPIC/Albany/imec cycles and improve PPA/tapeout.
What role does Intel's EMIB play in these accelerations?
Intel EMIB is accelerated by Synopsys tools, with EMIB-T in talks with Google and Amazon for AI chips using advanced packaging. This enables major customers to leverage EMIB-T later this year. It ties into UALink 2.0 and UCIe 3.0 for chiplet interconnects.
What new specifications has the UALink Consortium published?
UALink Consortium released four specifications for In-Network Compute, chiplets, manageability, and 200G performance with UCIe 3.0/200G PHY. This supports multi-die AI designs and data movement solutions like Baya fabrics. It aligns with Synopsys' $9.6B FY26 growth amid packaging talent shortages.
How is Synopsys contributing to 3DIC and advanced packaging?
Synopsys collaborates with Intel on EMIB-T packaging acceleration and offers multiphysics fusion for 3DIC design. DeepStack enables scalable design space exploration for advanced packaging like high-density hybrid bonding. This addresses STA/DVD profiling and yield binning for AI chiplets.
What challenges are highlighted in advanced packaging for AI?
Data movement bottlenecks persist despite UCIe/HBM4 interconnects and UALink advancements, with a packaging talent crunch noted. Innovations like chiplets and 3D integration drive performance but require EDA accelerations. Samsung invests $50M in Normal Computing for thermodynamic computing.
3-80x speedups: Cadence-NVIDIA 80x 3D-IC, Synopsys-NVIDIA/Ansys/Samsung STCO/3DIC 50% cut + DVD/Intel EMIB accel (EMIB-T Google/Amazon), UALink 2.0 In-Network Compute/UCIe 3.0/200G PHY, Samsung $50M Normal Computing thermodynamic, MediaTek/GTC 10x, ASML-Mistral 120x; DeepStack pkg exploration; UCIe/HBM4 chiplet interconnects; data movement bottlenecks (Baya fabrics/Arm ties). STA/DVD profiling/yield binning; shortens EPIC/Albany/imec; PPA/tapeout; Synopsys $9.6B FY26; packaging talent crunch. Ties to Nvidia-Marvell NVLink.