IBM + Lam at Albany: pushing sub-1nm logic with High-NA EUV and dry resist
Key Questions
What is the focus of the IBM and Lam Research collaboration in Albany?
IBM and Lam are developing sub-1nm logic using High-NA EUV and Aether dry resist with etch/deposition tools at their Albany facility, targeting March 2026. Milestones include TEL coater installation and ASML EXE arrival.
How does Intel's High-NA EUV rollout compare?
Intel plans High-NA EXE:5200 for high-volume manufacturing and EMIB-T rollout in 2026 for AI packages. This aims to close gaps with TSMC CoWoS, amid talks with Google and Amazon.
What are the key challenges in High-NA EUV lithography?
Challenges include litho-etch control for CD, LER, overlay, STA, and DVD, addressed by Synopsys EMIB acceleration. Risks involve High-NA adoption, helium supply, and Inprentus tools.
What role does Albany play in semiconductor innovation?
Albany is a hub for next-generation chipmaking, with IBM/Lam pushing sub-1nm nanosheet tech. New York is positioning it as a leader through facilities like this and Intel's involvement.
How is Intel competing for AI silicon business?
Intel is in talks with Google and Amazon to supply AI chips using advanced packaging like EMIB-T. This strategy aims to win business from TSMC amid capacity shortages.
IBM/Lam Albany (Mar 2026) High-NA EUV/Aether sub-1nm/nanosheet w/ etch/depo tools; milestone TEL coater install/ASML EXE arriving. Intel EXE:5200 HVM/EMIB-T 2026 rollout for AI pkgs vs TSMC CoWoS gaps, Google/Amazon Rio Rancho/Penang $1B+ rev. Litho-etch CD/LER/overlay/STA/DVD + Synopsys EMIB accel. Risks: High-NA/He/Inprentus.